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BMI1 (BMI),
an x86-64 expansion of bit-manipulation instructions by Intel, introduced in conjunction with the Advanced Vector Extensions SIMD instruction set. With the Bulldozer microarchitecture, BMI1 as well as AVX are also available on AMD processors under the initial name BMI, along with their Trailing Bit Manipulation Instructions (TBM) [1]. Most BMI1 instructions (except LZCNT and TZCNT) employ the VEX prefix encoding to support up to three-operand syntax with non-destructive source operands on 32- or 64-bit general-purpose registers. BMI1 (ANDN, BEXTR, BLSI, BLSMK, BLSR, TZCNT) requires bit 3 set in EBX of CPUID with EAX=07H, ECX=0H. LZCNT, not exactly member of BMI1, requires bit 5 set in ECX of CPUID EAX=80000001H. With the advent of AVX2, some more bit-twiddling on general-purpose registers is proposed with BMI2.

Instructions

BMI1 instructions may speedup various bitboard operations, such as relative complement, and isolation, reset and separation of the least significant one bit, they combine two instructions and reduce register pressure. Leading and trailing zero count are useful for scanning bits with possibly empty sets.

ANDN

Logical And Not, the relative complement, no intrinsic due to compiler support.
dest ::= ~src1 & src2;

BEXTR

Bit Field Extract [2]. Nice to extract some consecutive bits from a (rotated) occupancy bitboard, or, as they name suggests, from bit-field structures.
dest ::= (src >> start) & ((1 << len)-1);
 
unsigned __int32 _bextr_u32(unsigned __int32 src, unsigned __int32 start, unsigned __int32 len);
unsigned __int64 _bextr_u64(unsigned __int64 src, unsigned __int32 start, unsigned __int32 len);
A shiftless sign extension might be applied by [3]:
dest_signextended ::= (dest ^ signbit) - signbit

BLSI

Extract Lowest Set Isolated Bit [4], isolates least significant one bit.
dest ::= src & -src;
 
unsigned __int64 _blsi_u64(unsigned __int64 src);

BLSMSK

Get Mask Up to Lowest Set Bit [5], sets all bits below the least significant one bit, and clears all upper bits.
dest ::= (src-1) ^ src;
 
unsigned __int64 _blsmsk_u64(unsigned __int64 src);

BLSR

Reset Lowest Set Bit [6], resets least significant one bit.
dest ::= (src-1) & src;
 
unsigned __int64 _blsr_u64(unsigned __int64 src);

LZCNT

Count the Number of Leading Zero Bits [7], initially from AMD's SSE4a aka Advanced Bit Manipulations (ABM). If not supported, processor executes BSR [8] presumly with xor 63.
unsigned __int64 _lzcnt_u64(unsigned __int64 src);

TZCNT

Count the Number of Trailing Zero Bits [9]. If not supported, processor executes BSF [10].
unsigned __int64 _tzcnt_u64(unsigned __int64 src);

See also


Manuals


External Links


References

  1. ^ AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions (pdf)
  2. ^ _bextr_u32/64
  3. ^ Sign Extension from The Aggregate Magic Algorithms by Hank Dietz
  4. ^ _blsi_u32/64
  5. ^ _blsmsk_u32/64
  6. ^ _blsr_u32/64
  7. ^ _lzcnt_u32/64
  8. ^ Intel AVX and AVX2 Programming Reference (pdf), 7-14 LZCNT— Count the Number of Leading Zero Bits
  9. ^ _tzcnt_u32/64
  10. ^ Intel AVX and AVX2 Programming Reference (pdf), 7-27 TZCNT — Count the Number of Trailing Zero Bits
  11. ^ Moved BMI and TBM instructions from Volume 4 to Volume 3 in September 2011

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