A flip-flop or latch is a one bit memory. For instance a simple relay (K1) with its contact parallel to the On-push-button S2, "remembers" whether last action was pushing S1 (reset) or S2 (set) [2] .
A RS flip-flop is a pair of cross-coupled NAND or NOR-gates, where the outputs are feed back to the inputs. A D flip-flop, the most common flip-flop, stores the input D with the rising edge (0-1 transition) of a clock.
Random access memory is a fast form of computer memory and refers to the idea that any piece of data can be stored and retrieved in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.
Static RAM (SRAM) is an array of latches, where each latch has a unique address, which connects the addressed latch to its data-bus, often used as CPU cache.
Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically, which is the reason to call that memory dynamic. Since DRAM takes only one transistor and capacitor per bit, it is therefor used as cheap main memory part of recent computer data storage, despite its worse latency compared to SRAM.
Read-only memory (ROM) is a class of storage programmed once and mainly used to distribute firmware. EPROMs have a small quartz window which admits UV light for erasure [8] . ROM or EPROM were often embedded inside a microcontroller in conjunction with some RAM. They were often used in dedicated chess computers.
Todays processors utilize all the above types of memory from small and fast to large but slow within the concepts of virtual memory, paging, protection and various caches.
Ozalp Babaoglu, William Joy (1981). Converting a Swap-Based System to do Paging in an Architecture Lacking Page-Reference Bits. Proceedings of the 8th SOSP, Operating Systems Review, Vol. 15, No. 5, pp. 78-86
Subir Bhattacharya, Amitava Bagchi (1986). Making Best Use of Available Memory when Searching Game Trees. Proceedings of the 5th International Conference on Artificial Intelligence (AAAI-86), pp. 163-167. AAAI/MIT Press, Boston, MA.
Hermann Kaindl, G. Kainz, A. Leeb, H. Smetana (1995). How to use limited memory in heuristic search. Proceedings of the Fourteenth International Joint Conference on Artificial Intelligence (IJCAI-95), Montreal, Canada, pp. 236-242.
David Silver, Richard Sutton, Martin Müller (2008). Sample-Based Learning and Search with Permanent and Transient Memories. In Proceedings of the 25th International Conference on Machine Learning, pdf
Adriaan de Groot (1966). Perception and Memory versus Thought: Some Old Ideas and Recent Findings. Problem Solving: Research, Method, and Theory (ed. B. Kleinmuntz), pp. 19-50. John Wiley, New York.
A. Harry Klopf (1982). The Hedonistic Neuron: A Theory of Memory, Learning, and Intelligence. Hemisphere Publishing Corporation, University of Michigan
Fernand Gobet, Herbert Simon (1996). Templates in Chess Memory: A Mechanism for Recalling Several Boards. Cognitive Psychology, Vol. 31, pp. 1-40.
Fernand Gobet, Herbert Simon (1996). Recall of random and distorted positions: Implications for the theory of expertise. Memory & Cognition, 24, 493-503.
Fernand Gobet, Herbert Simon (1996). Recall of rapidly presented random chess positions is a function of skill. Psychonomic Bulletin & Review, 3, 159-163, word reprint
Fernand Gobet, Herbert Simon (1998). Expert chess memory: Revisiting the chunking hypothesis. Memory, 6, 225-255
Guillermo Campitelli, Fernand Gobet, Amanda Parker (2005). Structure and Stimulus Familiarity: A Study of Memory in Chess-Players with Functional Magnetic Resonance Imaging. The Spanish Journal of Psychology Vol. 8, No. 2, 238-245. pdf
Alan H. Bond (2005). Representing episodic memory in a system-level model of the brain. Neurocomputing, vol 65-66, pp. 261-273, pdf
Table of Contents
Flip-Flop
A flip-flop or latch is a one bit memory. For instance a simple relay (K1) with its contact parallel to the On-push-button S2, "remembers" whether last action was pushing S1 (reset) or S2 (set) [2] .A RS flip-flop is a pair of cross-coupled NAND or NOR-gates, where the outputs are feed back to the inputs. A D flip-flop, the most common flip-flop, stores the input D with the rising edge (0-1 transition) of a clock.
N-Bit Latches
N-Bit latches are arrays of one-bit latches or flip-flops typically as wide as a connected parallel data-bus. They may be used as a registers or scratchpad RAM inside a central processing unit.RAM
Random access memory is a fast form of computer memory and refers to the idea that any piece of data can be stored and retrieved in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.Static RAM
Static RAM (SRAM) is an array of latches, where each latch has a unique address, which connects the addressed latch to its data-bus, often used as CPU cache.Dynamic RAM
Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an electronic circuit. Since capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically, which is the reason to call that memory dynamic. Since DRAM takes only one transistor and capacitor per bit, it is therefor used as cheap main memory part of recent computer data storage, despite its worse latency compared to SRAM.Synchronous dynamic random access memory (SDRAM)
DDR SDRAM with Double data rate
ROM
Read-only memory (ROM) is a class of storage programmed once and mainly used to distribute firmware. EPROMs have a small quartz window which admits UV light for erasure [8] . ROM or EPROM were often embedded inside a microcontroller in conjunction with some RAM. They were often used in dedicated chess computers.Since each data-bit stored in a ROM is a boolean function of its inputs or address, a ROM is also used to implement combinatorial logic.
Auxiliary Storage
Beside the computer's random access main memory, auxiliary storage refer to mass storage like optical discs, and magnetic storage hard disk drives. Those devices are usually connected via a serial bus, and accessed via streams.USB 3.0
Historical Data Storage
Plated wire memory from Wikipedia
Memory Hierarchy
Memory Management
Todays processors utilize all the above types of memory from small and fast to large but slow within the concepts of virtual memory, paging, protection and various caches.Virtual Memory
Paging
Page table
Page replacement algorithm
Paging
Demand Paging
Page fault
Copy-on-write
TLB
Huge Pages
Note that what Windows calls "large pages," Linux and Unix call "huge pages" or "huge TLB pages (x86 and x86-64)Memory Model
Shared Memory
False sharing from Wikipedia
Cache
MSI protocol from Wikipedia
MESI protocol from Wikipedia
MOESI protocol from Wikipedia
assembly - The prefetch instruction - Stack Overflow
Data Prefetch Support - GNU Project - Free Software Foundation (FSF)
Software prefetching considered harmful by Linus Torvalds, LWN.net, May 19, 2011
Segmentation
Allocation
Manual memory management
Memory leak
Garbage collection
Memory Footprint
Beside their individual memory footprint, chess programs have to deal with huge memory areas of transposition table and possibly caches for endgame table- or bitbases and their relative huge random access latencies.Miles Davis, Wayne Shorter, Herbie Hancock, Ron Carter, Tony Williams
Monika Malczak, Mateusz Gramburg, Paweł Zwierzyński-Pióro, Michał Szeligowski
Multiprocessing
Memory versus Search
See also
Publications
Computer Memory
1960 ...
1970 ...
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Memory part 1
Memory part 2: CPU caches
Memory part 3: Virtual Memory
Memory part 4: NUMA support
Memory part 5: What programmers can do
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Cognition
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Forum Posts
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2010 ...
- Is a querying the hash tables such a huge bottleneck? by Oliver Uwira, CCC, October 28, 2010
2011- MSVC calloc question by Harm Geert Muller, CCC, March 17, 2011
2012- DNA data storage breaks records by Terry McCracken, CCC, August 18, 2012 [19]
2013- DrMemory: memory debugger tool for Windows (and Linux) by Martin Sedlak, CCC, January 22, 2013 » Debugging
- Multi-threaded memory access by ThinkingALot, OpenChess Forum, February 10, 2013 » Thread, Shared Hash Table
- Hybrid Memory Cube effect on computer chess by Albert Silver, CCC, April 05, 2013 [20]
- MEM_LARGE_PAGES by Alvaro Cardoso, CCC, September 18, 2013
- Multithreaded LRU by Alvaro Cardoso, CCC, October 06, 2013 » Endgame Tablebases
- tablebase caching / mmap() / page cache by Ronald de Man, CCC, October 13, 2013 » Endgame Tablebases, Syzygy Bases
- Table Base Cache Size question by Rob Nicholas, CCC, December 05, 2013 » Endgame Tablebases
20142015 ...
- Low-RAM engine by Harm Geert Muller, CCC, January 28, 2015
- The effect of dual channel RAM by Volker Annuss, CCC, March 01, 2015 » Arminius
- One hundred thirty gigabytes by Steven Edwards, CCC, July 03, 2015
- 3D XPoint by Edmund Moshammer, CCC, August 02, 2015 [22]
- Hash cache by Harm Geert Muller, CCC, October 12, 2015 » Hash Table, Transposition Table
2016- NUMA 101 by Robert Hyatt, CCC, January 07, 2016 » Parallel Search
- NUMA in a YBWC implementation by Edsel Apostol, CCC, July 20, 2016 » Young Brothers Wait Concept
- lets get the ball moving down the field on numa awareness by Mohammed Li, FishCooking, August 30, 2016 » NUMA, Stockfish, asmFish
- Tipical cache and branch misses for a chess engine by Nicu Ionita, CCC, September 14, 2016 » Avoiding Branches, Profiling
- What do you do with NUMA? by Matthew Lai, CCC, September 19, 2016 » NUMA
- L3 cache, RAM and other performance factors by Nimzy, Rybka Forum, December 04, 2016 » Playing Strength
2017External Links
Computer Memory
Gustavo Duarte's Blog
from Best Of by Gustavo Duarte:Cognition
Neuroscience
Misc
References
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