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Motorola_PowerPC_603_die.JPG

PowerPC, (Power (Performance optimization with enhanced RISC) Performance Computing)
a RISC architecture and ISA created by the 1991 AppleIBMMotorola alliance dubbed AIM, well known for being used by Apple's Power Macintosh lines from 1994 to 2006, IBM supercomputers, servers and workstations i.e. RS/6000, Pegasos, various Game consoles such as Xbox 360, Wii, still used inside the AmigaOne and AmigaOS 4 PCs and embedded systems.
Die shot of PowerPC 603 [1]

Architecture

Derived from the 1990 IBM POWER ISA with its POWER1 and POWER2 processors, the PowerPC architecture added 64-bit specification that is backward compatible with the 32-bit mode [2], and support for both big-endian and little-endian operation modes. 32-bit code will run natively unmodified on a 64-bit chip [3]. In the late 90s, PowerPC was extended by the 64-bit only PowerPC-AS ISA, and with advent of IBM's POWER4, PowerPC subsequently incorporated into the broader ISA superset and registered trademark governed by Power.org, the Power Architecture and POWER ISA. PowerPC CPUs have 32 general purpose registers, each either 32 bits or 64 bits in size depending on the chip, labelled r0 through r31. Integer instructions include Count Leading Zeros [4], starting at the most significant bit with number 0 aka big-endian bit emumeration [5].

Generations

G1 and G2

PowerPC 600 was the first generation of PowerPC, launching the PowerPC 601 in 1993 followed by the second generation PowerPC 603, PowerPC 604 and the first 64-bit PowerPC 620. The 620 features a five stage instruction pipeline - four instructions issued per clock, instruction dispatch in order, out-of-order execution, in-order completion - branch prediction with speculative execution, 32k data and 32k instruction cache - 8 set associative, physically addressed - and multiprocessor support with bus snooping for cache coherency (MESI). The 620 supports atomic operations (read/modify/write) with a pair of instructions, Load Word and Reserve (LWARX) and Store Conditional (STCX) [6] [7].

G3 and G4

Subsequent PowerPC designs were named and labeled by their apparent technology generation. That began with the G3 which was an internal project name inside AIM for the development of what would become the 32-bit PowerPC 750 family [8]. The fourth generation 32-bit PowerPC G4 (PowerPC 7400) debuted in August 1999 [9], and introduced AltiVec SIMD .

G5

The 64-bit PowerPC G5 (Apple) aka PowerPC 970 was introduced in 2002. The PowerPC 970 is a single core derivative of the dual POWER4. It has a hardware prefetch unit and a three way branch prediction unit, eight execution units: two ALUs, two double precision floating-point units, two load/store units and two AltiVec SIMD units.

Chess Programs

at times or exclusively dedicated to PowerPC

Operating Systems


See also


Publications


Forum Posts


External Links

Architectures

Processors

32-bit

64-bit

Assembly

Calling Conventions

MISC


References

  1. ^ Die shot of Motorola PowerPC 603 microprocessor (XPC603FE75-2B), by Pauli Rautakorpi, April 29 2014, CC BY 3.0, Wikimedia Commons
  2. ^ IBM PowerPC assembly
  3. ^ PowerPC Assembly tutorial
  4. ^ A data point for PowerPC bitboard program authors by Steven Edwards, CCC, May 09, 2005
  5. ^ IBM Knowledge Center - cntlzd (Count Leading Zeros Double Word) instruction
  6. ^ PowerPC 620 - Vorlesung Rechnerarchitektur, Heidelberg University (pdf)
  7. ^ x86 equivalent for LWARX and STWCX - Stack Overflow
  8. ^ PowerPC from Wikipedia
  9. ^ PowerPC G4 from Wikipedia
  10. ^ Re: A data point for PowerPC bitboard program authors by Robert Hyatt, CCC, May 09, 2005
  11. ^ The way that the PowerPC chips inside Deep Blue work in parallel to break down and solve a chess-board problem is a pretty good analog for the way many scientists, working independently, advance our total understanding of the universe, or genetics..., from IBM Research | Deep Blue | Overview
  12. ^ HIARCS 11.1 SP / MP Macintosh has arrived! by rafowell, CCC, April 03, 2007
  13. ^ MkLinux from Wikipedia

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