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SSE3 (Streaming SIMD Extensions 3), is Intel's third iteration for the SSE x86 instruction set, introduced in 2004 with the Prescott revision of the Pentium 4 CPU. In April 2005 AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The 13 new instructions are most processing vectors of floats or doubles, most notable horizontal add and sub inside one 128-bit xmm-register, LDDQU, an alternative misaligned load, which is even quite fast for loads that cross cacheline boundaries [1][2], and FISTTP, which is a new x87 instruction [3].

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References

  1. ^ LDDQU: Load Unaligned Integer 128 Bits (x86 Instruction Set Reference)
  2. ^ Unaligned memory operands - US Patent 6721866 Description
  3. ^ How to Implement the FISTTP Streaming SIMD Extensions 3 Instruction - IntelĀ® Software Network

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