Zeljko+Zilic

a Croatian electrical engineer and computer scientist, Associate Professor at McGill University. He holds a [|Bachelor of Engineering] from [|University of Zagreb] and received his Ph.D. and M.Sc. from the University of Toronto. His research interests covers [|logic synthesis], testing, verification and debug FPGA, [|embedded], [|wireless] and [|multiprocessor] systems as well as [|algebraic], [|combinatorial] and [|quantum algorithms]. || toc =Selected Publications=
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 * [[image:ZeljkoZilic.jpg width="153" height="200" link="http://www.iml.ece.mcgill.ca/people/professors/zilic/index.php"]] ||~  || **Zeljko Zilic**,
 * Zeljko Zilic ||~  ||^   ||
 * Marc Boulé, Zeljko Zilic (**2002**). //An FPGA Move Generator for the Game of Chess//. McGill University, [|pdf]
 * Marc Boulé, Zeljko Zilic (**2002**). //An FPGA Move Generator for the Game of Chess//. ICGA Journal, Vol. 25, No. 2, [|pdf]
 * Marc Boulé, Zeljko Zilic (**2003**). //FPGA Hardware Acceleration: From Chess Playing to Automated Theorem Proving//. poster presentation, Micronet 2003

=External Links=
 * [|Zeljko Zilic MACS Page]
 * [|Zilic, Z., Ph.D., P. Eng.] within Integrated Microsystems Laboratory of McGill University

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