Itanium

a family of 64-bit microprocessors by Intel that implement the [|IA-64] architecture originated by [|Hewlett-Packard] (HP) and later jointly developed by HP and Intel. While the early development started in 1989 by HP, Intel officially announced the name of the processor, Itanium, on October 4, 1999. The Itanium [|Merced] was released on June 2001, [|Itanium 2] McKinley and Madison in 2002 and 2003 respectively, the so far most recent [|Poulson] (Itanium 9500) in November 2012, and [|Kittson] planned for 2015. Initially intended as Intel's successor for x86 aka IA-32 architecture, AMD forced Intel to change priorities with x86-64. || toc =Architecture= IA-64 applies [|explicitly parallel instruction computing] (EPIC) which allows the processor to execute multiple instructions in each clock cycle. EPIC implements a form of [|very long instruction word] (VLIW) architecture, in which a single instruction word contains up to three instructions. With EPIC, the compiler determines in advance which instructions can be executed at the same time, rather than the processor itself. The architecture implements [|branch predication] and [|speculation], has 128 64-bit general purpose registers, 128 82-bit floating point or SIMD registers, 64 one-bit predicates, and eight branch registers, and thirty functional execution units in eleven groups, such as various ALUs, SIMD units with parallel shift and multiply, and population count unit.
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 * [[image:Intel-Itanium-Processor-9500.jpg width="199" height="326" link="http://wccftech.com/intel-itanium-kittson-ia64-processors-32nm/"]] ||~  || **Itanium**,
 * Die shot of [|Itanium 9500] ||~  ||^   ||


 * [[image:Itanium_architecture.svg.png link="https://commons.wikimedia.org/wiki/File:Itanium_architecture.svg"]] ||
 * Itanium architecture ||

=x86 Support= x86 (IA-32) instructions were supported by hardware, and since 2006 emulated with the [|IA-32 Execution Layer].

=Chess Programs= TCSP, Tinker and Crafty were mentioned running under Itanium. While the original Merced was disappointing, Robert Hyatt reported a good performance of Crafty on McKinley in 2003, close to the Opteron with double frequency. Eugene Nalimov, at that time member of the Microsoft Visual compiler team targeting the Itanium platform, provided a IA-64 optimzed BitScan aka firstOne and lastOne in C, taking advantage of IA-64's [|branch predication].

=See also=
 * i860
 * x86
 * x86-64

=Forum Posts=
 * [|Re: What are the chances of getting a new 64bit instruction for chess :)] by Eugene Nalimov, CCC, June 27, 2000
 * [|Will the Itanium have a BSF or BSR instruction?] by Larry Griffiths, CCC, August 15, 2000 » BitScan
 * [|Itanium] by John Dahlem, CCC, January 17, 2001
 * [|Intel Itanium 2 Benchmarks] by Vincent Lejeune, CCC, May 29, 2002
 * [|Itanium2 Testing Crafty & Tinker Informal Results] by Brian Richardson, CCC, February 16, 2003
 * [|IA-64 vs OOOE (attn Taylor, Hyatt)] by Tom Kerrigan, CCC, February 11, 2003
 * [|Question: Itanium Info] by Slater Wold, CCC, December 08, 2003

=External Links=
 * [|Intel® Itanium® Processors]
 * [|Itanium from Wikipedia]
 * [|IA-64 from Wikipedia]
 * [|List of Intel Itanium microprocessors from Wikipedia]
 * [|How the Itanium Killed the Computer Industry] by [|John C. Dvorak], [|PCMag.com], January 26, 2009
 * [|Intel's Next Generation Itanium 'Kittson' IA64 Processor Detailed - 32nm Process, 9300/9500 Socket Compatible] by [|Usman Pirzada], April 2015

=References= =What links here?= include component="backlinks" page="Itanium" limit="40"
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