Cray-1

a [|supercomputer] designed, manufactured and marketed by [|Cray Research Inc.] since 1972. The first Cray-1 system was installed at Los Alamos National Laboratory in 1976 and it went on to become one of the best known and most successful supercomputers in history, it reigned as the world’s fastest from 1976 to 1982. Cray Research was founded by former [|Control Data Corporation] chief designer [|Seymour Cray], after CDC neglected to invest in Seymour Cray's [|CDC 8600] design. || toc =Architecture= The Cray-1 is a large-scale, general-purpose digital computer featuring scalar as well as [|vector processing], a 12.5 nanosecond clock period, and a 50 nanosecond memory cycle time. The basic configuration of the Cray-1 consists of the [|central processor unit] (CPU), one or more minicomputer [|consoles], and a [|mass storage] (disk) subsystem.
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 * [[image:Cray1Seymour.jpg width="255" height="316" link="http://www.computerhistory.org/revolution/supercomputers/10/7/3"]] ||~  || **Cray-1**,
 * [|Seymour Cray] in front of his Cray-1 ||~  ||^   ||

CPU
The CPU holds the ALU, memory, and [|I/O sections] of the computer. It is constructed from [|LSI chips] of high-speed [|ECL] [|bipolar junction transistors]. Memory is build from 1024-bit LSI chips of up to one [|mebi] 72-bit words, arranged in 16 banks. A word consists of 64 data bits and 8 check bits which allows [|single-error correction double-error detection] (SECDED).

Registers
Three primary [|register] sets consists of eight 24-bit [|address] registers (also loop counter, shift counts), eight 64-bit scalar registers, and eight vector registers, where one vector register is actually a set of 64 64-bit registers, called elements. Associated with the vector registers are a 7-bit vector length register and a 64-bit vector mask register to allow operations to be performed on individual vector elements.


 * [[image:cray_architecture.gif link="http://www.chrisfenton.com/homebrew-cray-1a/"]] ||
 * Register and ALU Block Diagram ||

Instructions
The Cray-1 executes 128 operation codes as either 16-bit (register reference) or 32-bit (memory reference) scalar or SIMD instructions. An integer multiply operation produces a 24-bit result, additions and subtractions either 24-bit or 64-bit results. Integer divide is not provided. The instruction set includes boolean operations for OR, AND, and exclusive OR and for a mask-controlled merge operation. Shift operations allow the manipulation of 64- or 128-bit operands to produce a 64-bit result. Instructions for scalar population and leading zero counts return bit counts based on scalar register contents to an address register.

The Cray design used [|pipeline parallelism] to implement vector instructions rather than multiple ALUs. In addition the design had completely separate pipelines for different instructions, for example, addition/subtraction was implemented in different hardware than multiplication. This allowed a batch of vector instructions themselves to be pipelined, a technique called vector chaining. The Cray-1 normally had a performance of about 80 [|MFLOPS], but with up to three chains running it could peak at 240 MFLOPS.

=Chess Programs=
 * Cray Blitz
 * Cube
 * Nuchess

=See also=
 * CDC 6600
 * CDC Cyber
 * Cray X-MP
 * Cray T3D
 * Cray T3E

=Manuals=
 * [|The CRAY-1 Computer System] (pdf)
 * [|CAL Assembly Reference Manual] (pdf)

=Publications=
 * Robert Hyatt (**1981**). //The Cray-1 Plays Chess (Part 1)//. Personal Computing, Vol. 5, No. 1, pp. 83
 * Robert Hyatt (**1981**). //The Cray-1 Plays Chess (Part 2)//. Personal Computing, Vol. 5, No. 2, pp. 95 » Cray Blitz
 * Robert Hyatt (**1981**). //[|Checkmate: The Cray-1 Plays Chess. Part 1]//. [|Cray Channels], Vol. 3, No. 1. [|pdf] from The Computer History Museum
 * Robert Hyatt (**1981**). //[|Checkmate: The Cray-1 Plays Chess. Part 2]//. [|Cray Channels], Vol. 3, No. 2. [|pdf] from The Computer History Museum
 * Robert Hyatt (**1983**). Cray Blitz - //A Computer Chess Playing Program//. Master's Thesis, University of Southern Mississippi
 * Harry Nelson (**1984**). //How We Won The Computer Chess World's Championship//. Excerpt from a talk given at he DAS Computer Science Colloquium, [|pdf] from The Computer History Museum » WCCC 1983

=Forum Posts=
 * [|hardware of Cray Blitz] by Leonid, CCC, June 13, 1999 » WCCC 1983
 * [|Cray Blity 1981?] by Joshua Lee, CCC, June 02, 2000 » ACM 1981
 * [|Cray and supercomputers (kinda long)] by Joshua Shriver, CCC, September 16, 2005
 * [|Homebrew Cray-1A] by Max May, CCC, September 01, 2010
 * [|FPGA Cray-1] by Dan Andersson, CCC, September 30, 2010
 * [|You'll need one of these to resurrect Cray Blitz] by Steven Edwards, CCC, May 01, 2012
 * [|Cray Blitz source (Carey)] by Robert Hyatt, CCC, September 10, 2008
 * [|How fast was the Cray?] by Sean Evans, CCC, September 23, 2016

=External Links= > [|Company History | Cray]
 * [|Cray-1 from Wikipedia]
 * [|Category: Cray-1 - Wikimedia Commons]
 * [|Cray (brand) from Wikipedia]
 * [|Cray, the Supercomputer Company | Cray"]
 * [|Cray Super Computers - Cray-1]
 * [|The Cray-1 Supercomputer - CHM Revolution] from The Computer History Museum
 * [|CRAY 1-A] from [|SCD Supercomputer Gallery]
 * [|Homebrew Cray-1A] by [|Chris Fenton]
 * [|Cray Operating System from Wikipedia]
 * [|Cray Time Sharing System from Wikipedia]
 * [|High Performance Computer Architectures: A Historical Perspective - The CRAY-1]
 * [|Die Cray 1 - Architektur eines Supercomputers] by [|Bernd Leitenberger] (German)
 * [|Cray-1 – the eight million dollar super-computer] by Frederic Friedel, ChessBase News, September 23, 2016 » Cray Blitz

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