MMX

toc =Register File= MMX uses eight 64-bit registers **MM0** through **MM7**, treated each as vector of eight bytes, four words, two double words or one quad word. The eight registers were aliased for the existing [|x87] FPU stack registers, and are therefor implicitly saved and restored during [|context switch] in existing operating systems. The drawback is, it is somewhat difficult to work with x87 floating point and MMX data in the same application, since the original [|emms-instruction] to switch the register file was relatively slow.
 * Home * Hardware * x86 * MMX**
 * [[image:http://upload.wikimedia.org/wikipedia/commons/thumb/5/5b/P-MMX.JPG/150px-P-MMX.JPG width="169" height="165" link="http://en.wikipedia.org/wiki/Intel_P5_%28microarchitecture%29"]] ||~  || **MMX** is a SIMD (Single instruction, multiple data) instruction set of x86 processors, starting in 1996 with Intel's [|Pentium MMX]. In 1998, AMD enhanced Intel's MMX with the [|3DNow!] extension, mostly related to the Float data type. MMX instructions are available through Assembly language, inline assembly and C-Compiler intrinsics along with the [|_m64] intrinsic data type . ||
 * [|Pentium MMX 166 MHz] ||~  ||^   ||

=MMX and 64-bit Windows= Since 64-bit Windows applications merely use SSE for floating point arithmetic, there was some early confusion whether MMX/x87 registers are safe to use due to context switching. Quote from [|Agner Fog's] Calling conventions manual:

.

=Applications= Almost the same bitboard applications as mentioned in the SSE2 application samples are possible with MMX, despite with scalar bitboards rather than vector of two.

East Fill
For instance East Attacks based on SIMD-wise Fill by Subtraction. code format="cpp" __m64 eastAttacks (__m64 occ, __m64 rooks) { __m64 tmp; occ = _mm_or_si64 (occ, rooks);  //  make rooks member of occupied tmp = _mm_xor_si64(occ, rooks);  // occ - rooks tmp = _mm_sub_pi8 (tmp, rooks);  // occ - 2*rooks return _mm_xor_si64(occ, tmp);   // occ ^ (occ - 2*rooks) } code 

MMX Popcount
AMD's proposed Efficient 64-Bit Population Count using MMX, 3DNow! and inline assembly :

code format="cpp"
 * 1) include "amd3d.h"

__declspec (naked) unsigned int __stdcall popcount64 (unsigned __int64 v) { static const __int64 C55 = 0x5555555555555555; static const __int64 C33 = 0x3333333333333333; static const __int64 C0F = 0x0F0F0F0F0F0F0F0F; __asm { MOVD     MM0, [ESP+4] ;v_low PUNPCKLDQ MM0, [ESP+8] ;v MOVQ     MM1, MM0     ;v PSRLD    MM0, 1       ;v >> 1 PAND     MM0, [C55]   ;(v >> 1) & 0x55555555 PSUBD    MM1, MM0     ;w = v - ((v >> 1) & 0x55555555) MOVQ     MM0, MM1     ;w PSRLD    MM1, 2       ;w >> 2 PAND     MM0, [C33]   ;w & 0x33333333 PAND     MM1, [C33]   ;(w >> 2) & 0x33333333 PADDD    MM0, MM1     ;x = (w & 0x33333333) + ((w >> 2) & 0x33333333) MOVQ     MM1, MM0     ;x PSRLD    MM0, 4       ;x >> 4 PADDD    MM0, MM1     ;x + (x >> 4) PAND     MM0, [C0F]   ;y = (x + (x >> 4) & 0x0F0F0F0F) PXOR     MM1, MM1     ; 0 PSADBW   MM0, MM1     ;sum across all 8 bytes MOVD     EAX, MM0     ;result in EAX per calling ; convention FEMMS ;clear MMX state RET 8 ;pop 8-byte argument off } } code

=See also=
 * AltiVec
 * SIMD and SWAR Techniques
 * SSE2

=Manuals=

Intel

 * [|Intel Architecture Software Developer’s Manual, Volume 1: Basic Architecture] (pdf)

AMD

 * [|AMD Athlon Processor x86 Code Optimization Guide]
 * [|AMD 3DNow! Technology Manual TM] (pdf)
 * [|AMD64 Architecture Volume 5: 64-Bit Media and x87 Floating-Point Instructions] (pdf)

=Forum Posts=
 * [|Using mmx instructions] by Frans Morsch, [|comp.lang.asm.x86], February 03, 2000
 * [|Re: Atomic write of 64 bits] by Frans Morsch, [|comp.lang.asm.x86], September 25, 2000
 * [|Re: Chezzz 1.0.1 - problem solved - for David Rasmussen] by David Rasmussen, CCC, February 05, 2003 » Population Count, Chezzz

=External Links=
 * [|MMX (instruction set) from Wikipedia]
 * [|MMX Technology Intrinsic Groups]
 * [|Chapter Eleven - The MMX Instruction Set] from [|The Art of Assembly Language Programming and HLA] by [|Randall Hyde]
 * [|Agner Fog's manuals]
 * [|Agner`s CPU blog] by [|Agner Fog]
 * [|Intel Intrinsics Guide]

=References= =What links here?= include page="MMX" component="backlinks" limit="60"
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