Combinatorial+Logic

toc =Implementation= In hardware, combinatorial logic can either realized with hardwired [|gates] of certain [|logic families] or [|programmable logic devices]. If the number of inputs is reasonable small, a once programmed ROM or [|LUT] can act as combinatorial logic. The inputs are the address, while one output is associated with a data-pin. In software this is like performing ALU-operations versus a memory lookup with pre-calculated outputs for all relevant inputs, related to the space-time tradeoff.
 * Home * Hardware * Combinatorial Logic**
 * [[image:Half_Adder.svg.png link="https://en.wikipedia.org/wiki/Half_adder"]] ||~  || A **Combinatorial Logic** (also Combinational Logic) is a [|digital circuit] where one or more outputs are [|boolean functions] of multiple inputs. The basic boolean operations [|conjunction], [|disjunction] and [|logical negation] are sufficient to derive all other boolean as well as arithmetical operations. Opposed to a sequential logic, outputs are not dependent on their history, that is a combinatorial logic does not require memory. ||
 * [|half adder circuit diagram] ||~  ||^   ||

=Basic Operations= 

AND
An [|AND gate] implements a [|logical conjunction]. math a\wedge b math

Truth Table

 * ~ - a - ||~ - b - ||  ||~ a and b ||
 * = 0 ||= 0 ||  ||= 0 ||
 * = 0 ||= 1 ||  ||= 0 ||
 * = 1 ||= 0 ||  ||= 0 ||
 * = 1 ||= 1 ||  ||= 1 ||

Symbols and Circuits

 * [[image:120px-AND_ANSI_Labelled.svg.png link="https://en.wikipedia.org/wiki/AND_gate"]] || [[image:220px-Diode-AND2.png link="https://en.wikipedia.org/wiki/Diode_logic"]] || [[image:200px-Relay_and.svg.png link="http://de.wikipedia.org/wiki/Und-Gatter"]] ||

OR
An [|OR gate] implements a [|logical disjunction]. math a\vee b math

Truth Table

 * ~ - a - ||~ - b - ||  ||~ a or b ||
 * = 0 ||= 0 ||  ||= 0 ||
 * = 0 ||= 1 ||  ||= 1 ||
 * = 1 ||= 0 ||  ||= 1 ||
 * = 1 ||= 1 ||  ||= 1 ||

Symbols and Circuits

 * [[image:120px-OR_ANSI_Labelled.svg.png link="https://en.wikipedia.org/wiki/OR_gate"]] || [[image:220px-Diode-OR2.png link="https://en.wikipedia.org/wiki/Diode_logic"]] || [[image:200px-Relay_or.svg.png link="http://de.wikipedia.org/wiki/Oder-Gatter"]] ||

NOT
A [|NOT gate] or **Inverter** implements a [|logical negation]. math \neg a math

Truth Table

 * ~ - a - ||  ||~ not a ||
 * = 0 ||  ||= 1 ||
 * = 1 ||  ||= 0 ||

Symbols and Circuits

 * [[image:128px-Not-gate-en.svg.png link="https://en.wikipedia.org/wiki/NOT_gate"]] || [[image:70px-NMOS_NOT.png link="https://en.wikipedia.org/wiki/NOT_gate"]] || [[image:Relay_not.svg.png link="http://de.wikipedia.org/wiki/Nicht-Gatter"]] ||

=Derived Operations= Concrete electronic gates often combine AND and OR with trailing NOT for so called [|NAND] and [|NOR gates]. As application of De Morgan's laws a NAND can also be interpreted as OR of inverted inputs, and NOR as AND of inverted inputs. 

NAND
A [|NAND gate] is the inversion of AND, NOT AND. math \neg (a\wedge b) math

Truth Table

 * ~ - a - ||~ - b - ||  ||~ not(a and b) ||
 * = 0 ||= 0 ||  ||= 1 ||
 * = 0 ||= 1 ||  ||= 1 ||
 * = 1 ||= 0 ||  ||= 1 ||
 * = 1 ||= 1 ||  ||= 0 ||

Symbols and Circuits

 * [[image:120px-NAND_ANSI_Labelled.svg.png link="https://en.wikipedia.org/wiki/NAND_gate"]] || [[image:200px-TTL_npn_nand.svg.png link="https://en.wikipedia.org/wiki/NAND_gate"]] || [[image:200px-Relay_nand.svg.png link="http://de.wikipedia.org/wiki/NAND-Gatter"]] ||

NOR
A [|NOR gate] is the inversion of OR, NOT OR. math \neg (a\vee b) math

Truth Table

 * ~ - a - ||~ - b - ||  ||~ not(a or b) ||
 * = 0 ||= 0 ||  ||= 1 ||
 * = 0 ||= 1 ||  ||= 0 ||
 * = 1 ||= 0 ||  ||= 0 ||
 * = 1 ||= 1 ||  ||= 0 ||

Symbols and Circuits

 * [[image:120px-NOR_ANSI_Labelled.svg.png link="https://en.wikipedia.org/wiki/NOR_gate"]] || [[image:NMOS_NOR.png link="https://en.wikipedia.org/wiki/NOR_gate"]] || [[image:200px-Relay_nor.svg.png link="http://de.wikipedia.org/wiki/NOR-Gatter"]] ||

XOR
A [|XOR gate] implements a [|exclusive disjunction], which might be derived from AND/OR/NOT, for instance from four NAND gates.

Truth Table

 * ~ - a - ||~ - b - ||  ||~ a xor b ||
 * = 0 ||= 0 ||  ||= 0 ||
 * = 0 ||= 1 ||  ||= 1 ||
 * = 1 ||= 0 ||  ||= 1 ||
 * = 1 ||= 1 ||  ||= 0 ||

Symbols and Circuits

 * [[image:128px-XOR_ANSI.svg.png link="https://en.wikipedia.org/wiki/XOR_gate"]] || [[image:300px-XOR_from_NAND.svg.png link="https://en.wikipedia.org/wiki/XOR_gate"]] || [[image:200px-Relay_xor.svg.png link="http://de.wikipedia.org/wiki/XOR-Gatter"]] ||

=DNF and CNF= Combinational logic can visualized by [|truth tables] and the construction is generally done using [|disjunctive] (sum of products) or [|conjunctive normal form] (products of sums), and using [|boolean algebra] or [|Karnaugh maps] to simplify the expression.  =ALU= Combinatorial logic is a huge part of the [|arithmetic logic unit] (ALU) of [|processors], which provides accordant boolean logical instructions working on all bits of a register in parallel as mentioned in General Setwise Operations of Bitboards. Therefor each Combinatorial Logic can of course emulated in software. 

Adder
A [|half adder] performs an addition on two one-bit binary numbers. Output of an AND gate is the carry, while a XOR gate leaves the one-bit sum. A [|full adder] with tad more gates adds three one-bit binary numbers, the third usually to feed in the carry from the previous digit, usually in [|carry look ahead] architectures, such as [|Kogge-Stone adder], also mentioned as parallel prefix algorithm.


 * [[image:Full-adder_logic_diagram.svg.png link="https://en.wikipedia.org/wiki/Half_adder#Full_adder"]] ||
 * [|Full Adder] ||
 * [[image:500px-4-bit_carry_lookahead_adder.svg.png link="https://en.wikipedia.org/wiki/Adder_%28electronics%29#Carry_look-ahead_adders"]] ||
 * [|4-bit adder] with [|Carry Look Ahead] ||
 * [|4-bit adder] with [|Carry Look Ahead] ||



Combinatorial Attacks
Assuming there are 13 times 64 digital inputs from a hardware wired chessboard. The 13 inputs per square has one exclusive "one" signal for either one of the twelve pieces or an empty signal. For each square a number of attacks/defend outputs may be defined to implement a huge Combinatorial Logic as a "zero cycle" attack table, i. e. output //a8 is attacked from south by white rook// as DNF (sum of products).

C Syntax
With C-like operators, that is '&' for AND and '|' for OR, the DNF would look like this: code southAttackByWhiteRook(a8) ::= wrook(a7) code
 * ( empty(a7) & wrook(a6) )
 * ( empty(a7) & empty(a6) & wrook(a5) )
 * ( empty(a7) & empty(a6) & empty(a5) & wrook(a4) )
 * ( empty(a7) & empty(a6) & empty(a5) & empty(a4) & wrook(a3) )
 * ( empty(a7) & empty(a6) & empty(a5) & empty(a4) & empty(a3) & wrook(a2) )
 * ( empty(a7) & empty(a6) & empty(a5) & empty(a4) & empty(a3) & empty(a2) & wrook(a1) )

Circuit
The same sample as circuit f. i. in [|Diode logic] with 34 [|diodes] and 7 [|resistors]: code Board bus empty                   white rook a1 a2 a3 a4 a5 a6 a7 a8 a1 a2 a3 a4 a5 a6 a7 a8      ANDs (MIN)         OR (MAX) | |  |  |  |  |  |  |   |  |  |  |  |  |  |  |		       |  |  |  |  |  |      |  |  |  |  |  |  |			       o--|--|--|--|--|--|--|--|--|--|--|--|--|<|-o---| R1 |---o +Vcc o--|--|--|--|--|--|--|--|--|--|--|--|<|-| | o--|--|--|--|--|--|--|--|--|--|--|<|-|  D1-D7 | |  o--|--|--|--|--|--|--|--|--|--|<|-| | |  |  o--|--|--|--|--|--|--|--|--|<|-| | |  |  |  o--|--|--|--|--|--|--|--|<|-| | |  |  |  |      o--|--|--|--|--|--|--|<|-o--|>|--o  D28 | |  |  |  |         |  |  |  |  |  |                                      |       o--|--|--|--|-|--|--|--|--|--|--|<|-o---| R2 |---o +Vcc | o--|--|--|-|--|--|--|--|--|--|<|-|                  | | o--|--|-|--|--|--|--|--|--|<|-|  D8-D13           | | |  o--|-|--|--|--|--|--|--|<|-|                   | | |  |  o-|--|--|--|--|--|--|<|-|                   | | |  |  |         o--|--|--|--|--|--|<|-o--|>|--o  D29 | |  |  |            |  |  |  |  |                                      |          o--|--|--||--|--|--|--|--|<|-o---| R3 |---o +Vcc | o--|--||--|--|--|--|--|<|-|                  | | o--||--|--|--|--|--|<|-|  D14-18           | | |  o|--|--|--|--|--|<|-|                   | | |  |            o--|--|--|--|--|<|-o--|>|--o  D30 | |  |               |  |  |  |                                      |             o--|--|---|--|--|--|--|<|-o---| R4 |---o +Vcc | o--|---|--|--|--|--|<|-| D19-D22          | | o---|--|--|--|--|<|-|                   | | |               o--|--|--|--|<|-o--|>|--o  D31 | |                  |  |  |                                      |                o--|--|--|--|--|<|-o---| R5 |---o +Vcc | o--|--|--|--|<|-| D23-D25          | |                 o--|--|--|<|-o--|>|--o  D32 |                    |  |                                      |                   o-|--|--|<|-o---| R6 |---o +Vcc | | |                  |  D26-D27          | o--|--|<|-o--|>|--o D33 |                                     |  D34 o--o--|>|--o-->--o a8 attacked |      by white rook _      from south | | R7                                                                                  |_| |                                                                                --o-- ---  gnd - code

=See also=
 * Belle | Hardware Move Generation
 * CHEOPS
 * General Setwise Operations
 * Sequential Logic

=External Links= > [|AND gate] > [|OR Gate] > [|NOT Gate] > [|NAND gate] > [|NOR gate] > [|XOR gate] > [|XNOR gate] > [|Fredkin gate] > [|Toffoli gate] > [|Relay] > [|Diode logic] > [|Resistor–transistor logic] > [|Diode–transistor logic] > [|Transistor–transistor logic] > [|Emitter-coupled logic] > [|Complementary metal–oxide–semiconductor] > [|Integrated injection logic] > media type="youtube" key="wIRxe_gcwVc"
 * [|Combinational logic from Wikipedia]
 * [|Combinational Logic & Systems Tutorial Guide]
 * [|Proposition (disambiguation) from Wikipedia]
 * [|Propositional calculus from Wikipedia]
 * [|Logic gate from Wikipedia]
 * [|Logic family from Wikipedia]
 * [|Address decoder from Wikipedia]
 * [|Lookup table from Wikipedia]
 * [|Curved Air] - [|Propositions] (1971), [|YouTube] Video

=References= =What links here?= include page="Combinatorial Logic" component="backlinks" limit="80"
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