PowerPC

a [|RISC] [|architecture] and [|ISA] created by the 1991 Apple–IBM–Motorola alliance dubbed [|AIM], well known for being used by Apple's Power Macintosh lines from 1994 to 2006, IBM [|supercomputers], [|servers] and [|workstations] i.e. [|RS/6000], [|Pegasos], various [|Game consoles] such as [|Xbox 360], [|Wii], still used inside the AmigaOne and [|AmigaOS 4] PCs and [|embedded systems]. || toc =Architecture= Derived from the 1990 [|IBM POWER ISA] with its [|POWER1] and [|POWER2] processors, the PowerPC architecture added 64-bit specification that is backward compatible with the 32-bit mode, and support for both big-endian and little-endian operation modes. 32-bit code will run natively unmodified on a 64-bit chip. In the late 90s, PowerPC was extended by the 64-bit only **PowerPC-AS** ISA, and with advent of IBM's [|POWER4], PowerPC subsequently incorporated into the broader ISA superset and registered trademark governed by [|Power.org], the [|Power Architecture] and POWER ISA. PowerPC CPUs have 32 general purpose registers, each either 32 bits or 64 bits in size depending on the chip, labelled r0 through r31. Integer instructions include Count Leading Zeros, starting at the most significant bit with number 0 aka big-endian bit emumeration.
 * Home * Hardware * PowerPC**
 * [[image:Motorola_PowerPC_603_die.JPG link="https://commons.wikimedia.org/wiki/File:Motorola_PowerPC_603_die.JPG"]] ||~ || **PowerPC**, (Power (Performance optimization with enhanced RISC) Performance Computing)
 * Die shot of PowerPC 603 ||~ ||^ ||

=Generations=

G1 and G2

 * PowerPC 600** was the first generation of PowerPC, launching the PowerPC 601 in 1993 followed by the second generation PowerPC **603**, PowerPC **604** and the first 64-bit PowerPC **620**. The 620 features a five stage [|instruction pipeline] - four instructions issued per clock, instruction dispatch in order, [|out-of-order execution], in-order completion - [|branch prediction] with [|speculative execution], 32k data and 32k instruction cache - 8 set associative, physically addressed - and [|multiprocessor] support with [|bus snooping] for [|cache coherency] ([|MESI]). The 620 supports [|atomic operations] ([|read/modify/write])  with  a  pair  of  instructions, Load Word and Reserve  (LWARX) and Store Conditional (STCX).

G3 and G4
Subsequent PowerPC designs were named and labeled by their apparent technology generation. That began with the **G3** which was an internal project name inside AIM for the development of what would become the 32-bit [|PowerPC 750 family]. The fourth generation 32-bit [|PowerPC G4] (PowerPC 7400) debuted in August 1999, and introduced AltiVec SIMD. 

G5
The 64-bit **PowerPC G5** (Apple) aka [|PowerPC 970] was introduced in 2002. The PowerPC 970 is a single core derivative of the dual [|POWER4]. It has a hardware [|prefetch unit] and a three way [|branch prediction unit], eight execution units: two ALUs, two double precision floating-point units, two load/store units and two AltiVec SIMD units.

=Chess Programs= at times or exclusively dedicated to PowerPC
 * Arthur
 * Crafty
 * Deep Blue ([|RS/6000])
 * Hiarcs 11
 * Innovation
 * MacChess
 * McTobber
 * The Sniper
 * Wii Chess
 * Zugzwang

=Operating Systems=
 * [|AmigaOS 4 from Wikipedia]
 * Linux
 * Mac OS
 * UNIX (AIX)
 * [|WarpOS from Wikipedia]
 * Windows NT

=See also=
 * AltiVec
 * Macintosh

=Publications=
 * [|M.C. Becker], [|C.R. Moore], et al. (**1993**). //[|The PowerPC 601 microprocessor]//. IEEE Micro '93
 * [|M.S. Allen], [|M.C. Becker] (**1993**). //Multiprocessing aspects of the PowerPC 601//. IEEE [|CMPCON 1993]
 * [|Trung A. Diep], [|Christopher Nelson], [|John Paul Shen] (**1994**). //[|Performance Evaluation of the PowerPC 620 Microarchitecture]//. Carnegie Mellon University, [|pdf]
 * [|D. Levitan], T. Thomas, P. Tu (**1995**). //The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor//. IEEE COMPCON '95
 * [|Michael Koerner], [|Ming Fai Chak], [|Joe Ruthven] (**1995**). //PowerPC - An Inside View//. IBM, [|pdf]

=Forum Posts=
 * [|G4 & AltiVec] by Will Singleton, CCC, October 04, 1999 » AltiVec
 * [|Mac G4 versus Pentium III] by Mark Andreoli, CCC, November 16, 1999 » x86
 * [|PowerPC BitCounting Functions Speed] by William Bryant, CCC, April 20, 2000 » Population Count
 * [|powerpc 4 @ 1.3ghz] by Rajen Gupta, CCC, October 07, 2001
 * [|An efficiency comparison data point for x86 vs PowerPC] by Steven Edwards, CCC, August 22, 2003
 * [|A data point for PowerPC bitboard program authors] by Steven Edwards, CCC, May 09, 2005 » BitScan

=External Links=

Architectures

 * [|PowerPC from Wikipedia]
 * [|PowerPC Architecture Book, Version 2.02] (IBM)
 * [|IBM POWER Instruction Set Architecture | Wikipedia]
 * [|Power Architecture from Wikipedia]

Processors

 * [|IBM POWER microprocessors from Wikipedia]

32-bit

 * [|PowerPC 600 from Wikipedia]
 * [|PowerPC 7xx from Wikipedia] (PowerPC G3)
 * [|Gekko (microprocessor) from Wikipedia]
 * [|Broadway (microprocessor) from Wikipedia]
 * [|MPC5xx from Wikipedia]
 * [|PowerPC G4 from Wikipedia]
 * [|PowerPC 400 from Wikipedia]
 * [|PowerPC e200 from Wikipedia]

64-bit

 * [|PowerPC 620 from Wikipedia]
 * [|POWER3 from Wikipedia]
 * [|PowerPC 970 from Wikipedia] (PowerPC G5)
 * [|Inside the IBM PowerPC 970 | Part I: Design Philosophy and Front End] by [|Jon Stokes], [|Ars Technica], October 29, 2002
 * [|Inside the IBM PowerPC 970 | Part II: The Execution Core] by [|Jon Stokes], [|Ars Technica]
 * [|POWER4 from Wikipedia]
 * [|POWER5 from Wikipedia]
 * [|Xenon (processor) from Wikipedia]

Assembly

 * [|Simplified PowerPC Instruction Set]
 * [|IBM PowerPC assembly]
 * [|PowerPC Assembly tutorial]

Calling Conventions

 * [|32-bit PowerPC Function Calling Conventions] (Apple)
 * [|64-bit PowerPC Function Calling Conventions] (Apple)

MISC

 * [|Macintosh Programmer's Workshop from Wikipedia] » Macintosh
 * [|Universal binary from Wikipedia] » x86, x86-64

=References= =What links here?= include component="backlinks" page="PowerPC" limit="40"
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