SSE3

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 * SSE3** (Streaming SIMD Extensions 3), is Intel's third iteration for the SSE x86 instruction set, introduced in 2004 with the [|Prescott] revision of the [|Pentium 4] CPU. In April 2005 AMD introduced a subset of SSE3 in revision E ([|Venice] and [|San Diego]) of their [|Athlon 64] CPUs. The 13 new instructions are most processing vectors of floats or doubles, most notable horizontal add and sub inside one 128-bit xmm-register, LDDQU, an alternative misaligned load, which is even quite fast for loads that cross cacheline boundaries, and FISTTP, which is a new [|x87] instruction.

=See also=
 * AltiVec
 * AVX
 * MMX
 * SIMD and SWAR Techniques
 * SSE
 * SSE2
 * SSSE3
 * SSE4
 * SSE5
 * x86-64
 * XOP

=Publications=
 * Daisuke Takahashi (**2007**). //[|An Implementation of Parallel 1-D FFT Using SSE3 Instructions on Dual-Core Processors]//. Proc. Workshop on State-of-the-Art in Scientific and Parallel Computing (PARA 2006), Lecture Notes in Computer Science, No. 4699, pp. 1178-1187, [|Springer]

=External Links=
 * [|SSE3 from Wikipedia]
 * [|Intel(R) C++ Compiler User and Reference Guides] covers Intrinsics
 * [|SSE SSE2 and SSE3 for GNU C++ - Stack Overflow]
 * [|SSEPlus Project] from [|AMD Developer Central]
 * [|SSEPlus Project Documentation]
 * [|Agner`s CPU blog] by [|Agner Fog]
 * [|Intel Intrinsics Guide]

=References= =What links here?= include page="SSE3" component="backlinks" limit="40"
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