Home * Hardware * Berkeley Chess Microprocessor
CampanileMtTamalpiasSunset-original.jpg

Berkeley Chess Microprocessor, (BCM)
a chess microprocessor developed by James Testa and Alvin M. Despain at University of California, Berkeley [1] , introduced in May 1990 at the Custom Integrated Circuits Conference [2], also mentioned in Marc Boulé's 2002 thesis [3].

The BCM was a 200,000 transistor VLSI chip, 1.2 micron CMOS die, 11 mm by 9 mm in area, able to generate three million legal moves per second. The chip incorporates a move generator, a basic positional evaluator and search control, can detect pins and X-ray attacks, and has an ALU for each square to sum the values of attacking pieces to perform a kind of parallel SEE for move ordering and evaluation purposes such as mobility and square control.
The Campanile, UC Berkeley [4]

Move Generation

While the move generation design is similar to Belle's, legal move generation in hardware was already designed by Alvin Despain in the 70s, as described by Ozalp Babaoglu in his 1977 thesis [5] , but as noted by Joe Condon and Ken Thompson, never obtained funding for full construction [6] . Both, attackers and victims, emit signals in all directions simultaneously so that it is a matter of combinatorial logic in the square receivers to detect pins. Find victim and find attacker cycles use programmable priority arbiters for move ordering during full width as well as quiescence search. A 25–level ply stack to enable or disable origin- and target squares keeps track of the move generation stage, and controls which move is generated next. This is how the bookkeeping works in sequential C like pseudo code with Bitboards (omitting legal move logic):
disable[ply] = depth <= 0 ? emptySquares : 0; /* enable to-squares */
while ( ( to = findMVV(disable[ply])) >= 0 ) {
  disable[ply] &= ~ownPieces;  /* enable all possible from-squares */
  while ( ( from = findLVA(disable[ply])) >= 0 ) {
    make(from, to);            /* ply++ */
    ....
    unmake(from, to);          /* ply-- */
    disable[ply] |= 1 << from; /* disable from-square */
  }
  disable[ply] |= 1 << to;     /* disable to-square */
}

Zerker

The Berkeley Chess Microprocessor lacked participation in computer chess competitions. A chess entity of BCM's co-author James Testa dubbed Zerker was registered for the ACM 1990 tournament, noted as promising newcomer, as it reported 7,000,000 moves per second [7], roughly three times faster than Deep Thought at that time. Unfortunately, a damage to the machine during shipment from California forced its withdrawal [8] [9], and it seems the project was later abandoned.

See also


Publications


References

  1. ^ James Testa, Alvin M. Despain (1990). A CMOS VLSI chess microprocessor. University of California, Berkeley, IEEE Custom Integrated Circuit Conference
  2. ^ Custom Integrated Circuits Conference, 1990, Proceedings of the IEEE 1990
  3. ^ Marc Boulé (2002). An FPGA Move Generator for the Game of Chess. Masters thesis, McGill University, (Supervisor: Zeljko Zilic, Co-Supervisor: Monty Newborn), pdf
  4. ^ The Campanile and Mt. Tamalpais from Memorial Stadium at sunset, 2006 by Tristan Harward, University of California, Berkeley - Wikipedia
  5. ^ Ozalp Babaoglu (1977). Hardware implementation of the legal move generation and relative ordering functions for the game of chess. Master's thesis, University of California, Berkeley
  6. ^ Joe Condon, Ken Thompson (1982). Belle Chess Hardware. Advances in Computer Chess 3, Reprinted (1988) in Computer Chess Compendium
  7. ^ The 21st Annual ACM North American Computer Chess Championship from The Computer History Museum, pdf
  8. ^ Quick moves claim computer-chess title - Free Online Library, November 24, 1990
  9. ^ Monty Newborn, Danny Kopec (1991). The 21st ACM North American Computer Chess Championship. Communications of the ACM, Vol. 34, No. 11, online

What links here?


Up one Level