Kurt Keutzer (1989). Three Competing Design Methodologies for ASIC's: Architectual Synthesis, Logic Synthesis, Logic Synthesis and Module Generation. DAC 1989[5]
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Kurt Keutzer (1991). Impact and Evaluation of Competing Implementation Media for ASIC's..DAC 1990
Kurt Keutzer (1991). The Need for Formal Verification in Hardware Design and What Formal Verification Has Not Done for Me Lately. TPHOLs 1991
an American electrical engineer, computer scientist and professor at the University of California, Berkeley. He received his Ph.D. in CS from Indiana University in 1984 and then joined AT&T Bell Laboratories. In 1991 he joined Synopsys, Inc. where he became CTO and senior vice-president of research, where he was involved in electronic design automation. His research group is currently focused on using parallelism to accelerate the training and deployment of deep neural networks for applications in computer vision, speech recognition, multimedia analysis, computational finance and computer games [1]. In 2015, along with his doctoral student Peter H. Jin, he published on a MCTS based Go playing program which uses convolutional networks in all parts, exploring the Monte-Carlo search tree using Thompson sampling and a convolutional network, and evaluates convolutional network based rollouts on a GPU [2], a revised version published at CG 2016.
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