SWAR as acronym for SIMD Within A Register was coined by Hank Dietz and Randy Fisher ^{[1]} . It is a processing model which applies SIMD parallel processing across sections of a CPU register, often vectors of smaller than byte-entities are processed in parallel prefix manner.

To apply addition and subtraction on vectors of bit-aggregates or bit-field structures within a general purpose register, one has to take care carries and borrows don't wrap around. Thus the need to mask of all most significant bits (H) and add in two steps, one 'add' with MSB clear and one add modulo 2 aka 'xor' for the MSB itself. For bytewise (rankwise) math inside a 64-bit register, H is 0x8080808080808080 and L is 0x0101010101010101.

SWAR add z = x + y
z =((x &~H)+(y &~H))^((x ^ y)& H)

SWAR sub z = x - y
z =((x | H)-(y &~H))^((x ^~y)& H)

SWAR average z =(x+y)/2 based on x + y =(x^y)+2*(x&y)
z =(x & y)+(((x ^ y)& ~L)>>1)

Home * Programming * SIMD and SWAR TechniquesSingle InstructionsonMultiple Data(SIMD), namely on vectors of floats, doubles or various integers, bytes, words, double words or quad words, available through assembly and compiler intrinsics. SIMD-applications related to computer chess cover bitboard computations and fill-algorithms like Dumb7Fill and Kogge-Stone Algorithm, as well as evaluation related stuff, like this SSE2 dot-product of 64 bits by a vector of 64 bytes.SWARas acronym for SIMD Within A Register was coined by Hank Dietz and Randy Fisher^{[1]}. It is a processing model which applies SIMD parallel processing across sections of a CPU register, often vectors of smaller than byte-entities are processed in parallel prefix manner.^{[2]}## Table of Contents

## SIMD Instruction Sets

^{[3]})## SWAR Arithmetic

To apply addition and subtraction on vectors of bit-aggregates or bit-field structures within a general purpose register, one has to take care carries and borrows don't wrap around. Thus the need to mask of all most significant bits (H) and add in two steps, one 'add' with MSB clear and one add modulo 2 aka 'xor' for the MSB itself. For bytewise (rankwise) math inside a 64-bit register, H is 0x8080808080808080 and L is 0x0101010101010101.## Samples

Amazing, how similar these two SWAR- and parallel prefix wise routines are. Mirror horizontally and population count have in common to act on vectors of duos, nibbles and bytes. One swaps bits, duos and nibbles, while the second adds populations of them.## Publications

1999).AltiVec Revealed. MacTech, Vol. 15, No. 72009).SIMD Code Generation in Data-Parallel Programming. Ph.D. thesis, Saarland University, pdf^{[4]}, Jan Treibig, Gerhard Wellein (2013).The Practitioner's Cookbook for Good Parallel Performance on Multi- and Many-Core Systems. RRZE, SC13, slides as pdf## Manuals

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## NXP Semiconductors

^{[5]}## Intel

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