The TR 440 central processor (Zentraler Rechner), dubbed RD 441 [15], had four units (Werke), the instruction unit (Befehlswerk), accumulator based ALU (Rechenwerk), memory unit (Speicherwerk) and I/O-unit (Ein- Ausgabewerk) with 4 fast (used for data storage, drum memory ) and 12 standard I/O-channels (tapes, satellite computer), all four units connected by a priority unit (Vorrangwerk). The TR-4 compatible architecture used a word size of 52 bits, consisting of 48 data bits, 2 type bits (00 - floating point, 38 bit normalized mantissa, 01 - integer/fixed point (Ones' complement), 10 - opcode 2x24 bit, 11 - 8 six bit text characters) and 2 bit checksum (Dreierprobe). Instructions operate on words, half- and double words and bytes of 4, 6, 7 or 12 bits, as well as random word areas inside a register or memory.
a West-German general purpose 48-bit mainframe computer developed from 1964 until 1971 by Telefunken as successor of the TR-4, later manufactured by AEG Telefunken and Computer Gesellschaft Konstanz. The development team was headed by Eike Jessen [1]. The TR 440 introduced paging, multiple modes of operation, multiprocessing (two or three processors), vastly extended memory, satellite configurations (TR 86) and included innovative system software [2], as the time-sharing operating system BS3 [3] [4].
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Universities
A first TR 440 was shipped in 1969 to the Darmstadt German computing center. In total, 45 TR 440 computers were manufactured, many delivered to German universities during the early 70s [6], such as Ruhr University Bochum [7] , University of Düsseldorf, RWTH Aachen, University of Munich and Technical University of Munich via Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities [8] , University of Würzburg, University of Hamburg [9], Technical University of Berlin, University of Erlangen-Nuremberg, University of Tübingen, University of Stuttgart, University of Konstanz, Saarland University [10] , Kaiserslautern University of Technology [11] , University of Marburg [12] , Clausthal University of Technology and Helmholtz-Zentrum Geesthacht [13].Block Diagram
Architecture
The TR 440 central processor (Zentraler Rechner), dubbed RD 441 [15], had four units (Werke), the instruction unit (Befehlswerk), accumulator based ALU (Rechenwerk), memory unit (Speicherwerk) and I/O-unit (Ein- Ausgabewerk) with 4 fast (used for data storage, drum memory ) and 12 standard I/O-channels (tapes, satellite computer), all four units connected by a priority unit (Vorrangwerk). The TR-4 compatible architecture used a word size of 52 bits, consisting of 48 data bits, 2 type bits (00 - floating point, 38 bit normalized mantissa, 01 - integer/fixed point (Ones' complement), 10 - opcode 2x24 bit, 11 - 8 six bit text characters) and 2 bit checksum (Dreierprobe). Instructions operate on words, half- and double words and bytes of 4, 6, 7 or 12 bits, as well as random word areas inside a register or memory.Technology
Chess Programs
See also
Publications
External Links
TR 440
TR 440 Große Befehlsliste - Instruction Set List (pdf)
TR 440 images
TR 440 kernspeicher (core memory)
Computerwoche on TR 440
References
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