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		Yi-Fan Ke, a Taiwanese computer scientist, electrical engineer, chip designer and director of ASIC project development at Faraday Technology. He holds a Ph.D. from 1996 at National Taiwan University on parallel hardware architecture for accelerating computer chess system ^[1]. Along with his thesis advisor Tai-Ming Parng, Yi-Fan Ke further introduced the Guard Heuristic, which uses the control of squares to order and prune moves in Chess and Chinese Chess ^[2].
Yi-Fan Ke ^[3]

Selected Publications

^[4]

Yi-Fan Ke, Tai-Ming Parng (1993). The Guard Heuristic: Legal Move Ordering with Forward Game-Tree Pruning. ICCA Journal, Vol. 16, No. 2
Yi-Fan Ke (1996). A parallel hardware architecture for accelerating computer chess system-平行電腦象棋系統架構之設計及研究. Ph.D. thesis, National Taiwan University
Yi-Fan Ke, Tai-Ming Parng (1996). Parallel Move Generation System for Computer Chess. IEICE Transactions on Information and Systems, April, 1996, pp. 290-296
Yi-Fan Ke, Tai-Ming Parng (1996). A Parallel Hardware Architecture for Accelerating α-β Game Tree. IEICE Transactions on Information and Systems, September, 1996, pp. 1232-1240

External Links

^ Yi-Fan Ke (1996). A parallel hardware architecture for accelerating computer chess system-平行電腦象棋系統架構之設計及研究. Ph.D. thesis, National Taiwan University
^ Yi-Fan Ke, Tai-Ming Parng (1993). The Guard Heuristic: Legal Move Ordering with Forward Game-Tree Pruning. ICCA Journal, Vol. 16, No. 2
^ Yi-Fan Ke | LinkedIn
^ Yi-Fan Ke | LinkedIn

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